School of Computer and Information Sciences

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Browsing School of Computer and Information Sciences by Author "Abraham, Ajith"
  • Item
    Artificial bee colony algorithm for small signal model parameter extraction of MESFET
    ( 2010-01-01) Sabat, Samrat L. ; Udgata, Siba K. ; Abraham, Ajith
    This paper presents an application of swarm intelligence technique namely artificial bee colony (ABC) to extract the small signal equivalent circuit model parameters of GaAs metal extended semiconductor field effect transistor (MESFET) device and compares its performance with particle swarm optimization (PSO) algorithm. Parameter extraction in MESFET process involves minimizing the error, which is measured as the difference between modeled and measured S parameter over a broad frequency range. This error surface is viewed as a multi-modal error surface and robust optimization algorithms are required to solve this kind of problem. This paper proposes an ABC algorithm that simulates the foraging behavior of honey bee swarm for model parameter extraction. The performance comparison of both the algorithms (ABC and PSO) are compared with respect to computational time and the quality of solutions (QoS). The simulation results illustrate that these techniques extract accurately the 16-element small signal model parameters of MESFET. The efficiency of this approach is demonstrated by a good fit between the measured and modeled S-parameter data over a frequency range of 0.5- 25 GHz.© 2010 Elsevier Ltd. All rights reserved.
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    Dispersed harmony search algorithm for MESFET DC and small signal model parameter extraction
    ( 2012-06-01) Sabat, Samrat L. ; Udgata, Siba K. ; Coelho, Leandro D.Santos ; Abraham, Ajith ; Snasel, Vaclav
    This paper proposes a variant of harmony search algorithm named as dispersed harmony search (DHS) and its application to extract the drain current (DC) and small signal model parameters of Galium Arsenide (GaAs) metal extended semiconductor field effect transistor (MESFET). DHS algorithm is used to minimize the difference between measured and modeled (i) drain current to extract the DC model parameters and (ii) S-parameters to extract the small signal model parameters. The S-parameters are measured in the frequency range of 500 MHz to 25 GHz with a step of 500 MHz. The measured data are obtained from a fabricated MESFET of gate length 0.7 fim and gate width of 600 μm (4 × 150). The performance of DHS algorithm is compared with particle swarm optimization (PSO) and artificial bee colony (ABC) algorithm in terms of quality of solution and execution time to extract the model parameters. Comparison results reveal that the DHS algorithm has better convergence speed and also a robust technique for model parameter extraction compared with PSO and ABC algorithms. © 2012 ICIC International.
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    Field programmable gate arrays-based differential evolution coprocessor: A case study of spectrum allocation in cognitive radio network
    ( 2013-09-05) Anumandla, Kiran Kumar ; Peesapati, Rangababu ; Sabat, Samrat L. ; Udgata, Siba K. ; Abraham, Ajith
    In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T Field Programmable Gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorithm is implemented in the coprocessor whereas both fixed and floating point DE are implemented in the embedded processor. Performance of the coprocessor is evaluated by optimising benchmark functions of different complexities. The implementation results show that the coprocessor is 73.14-160.2× and 2.19-27.63× faster compared to the software execution time of the floating and fixed point algorithm respectively. As a case study, spectrum allocation problem of cognitive radio network is evaluated with the coprocessor. Results show an acceleration of 76.79-105× and 5.19-6.91× with respect to floating and fixed point DE in embedded processor. It is also observed that the application occupies 56% of BRAM, 54% of DSP48E, 16% of slice LUTs and maximum frequency of operation as 63.55 MHz in a Virtex-5 FPGA. This type of coprocessor is suitable for embedded applications where the fitness function remains unchanged. © The Institution of Engineering and Technology 2013.