Performance Investigation of Gate-Engineered Recessed-S/D FDSOI MOSFETs for Low Power Analog/RF Applications

Abstract

This paper explains the analog and RF performance of Gate-Engineered Recessed-Source/Drain (Re-S/D) Fully Depleted-Silicon on Insulator (FD-SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Re-S/D MOSFET has excellent capability of reducing series resistance which in turns improves the drive current capability and low leakages. In this paper, for the first time, the Analog and RF performance of Triple-Metal-Gate Re-S/D FD SOI MOSFET is analyzed to investigate the behavior of the device in Analog domain to be suggested for low power application. The device has been simulated using numerical 2-D device simulator from Silvaco ATLAS. The device performance has been evaluated with parameters such as drain current(Id), transconductance(gm), output conductance(gd), device capacitance(Cgs and Cgd), intrinsic gain(Av), early voltage(Vea), cut-off frequency(fT), transconductance frequency product(TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP).