Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications

Abstract

Fully-Depleted (FD) Silicon-on-Insulator (SOI) MOSFET has been attracting significant attention from the past two decades due to its excellent immunity over short-dimension effects. This paper investigates the short-channel characteristics of gate-stack (GS) triple-metal-gate (TMG) recessed-source/drain (Re-S/D) FD SOI-MOSFET for analog-applications. Furthermore, the suitability of the GS-TMG: Re-S/D FD SOI MOSFET in the analog domain has been examined on the basis of different figure-of-merit metrics, such as; transconductance, transconductance-efficiency-factor, and output-conductance. Simultaneously, the device reliability issues at different temperatures have also been taken under study. All these studies have been carried out on the basis of numerical simulations over TCAD-Silvaco (ATLAS™). The simulation results reveal that the studied nanoscaled GS-TMG: Re-S/D fully-depleted SOI-MOSFET exhibits enhanced immunity over short-dimension-effects with improved transconductance behavior. Also, the device offers switching ratio (Ion/Ioff) of 1011.