Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology

Abstract

Fully depleted silicon-on-insulator (FD SOI) technology has already been accepted for its short-channel immunity in nanoscale regime and the concept of metal-gate engineering has provided the flexibility to further scale-down the device dimensions. This paper presents the analog and radio-frequency behavior of hetero-gate-dielectric (HGD) triple-metal-gate (TMG) recessed-source/drain (Re-S/D) FD SOI MOSFET at 45-nm-technology node. Here, the analog performance has been investigated on the basis of numerical calculations of transconductance (gm), output conductance (gd), transconductance generation factor (TGF), and intrinsic gain (Av). Further, radio-frequency performance has been monitored by analyzing parasitic capacitances (Cgs and Cgd) and cutoff frequency (fT). All these studies have been performed using technology computer-aided design (TCAD) simulation tool Silvaco ATLAS. It is found that the proposed hetero-gate-dielectric-based TMG SOI MOSFET exhibits excellent transconductance behavior with higher gain and increased frequency of operation as compared to other state-of-the-art discussed in the literature. The proposed device offers cutoff frequency of 5.21 × 1011 Hz, which itself dictates the device immunity at high frequency. Simultaneously, the perspective of buried-oxide (BOX) thickness variation on the performance of HGD-TMG SOI MOSFET has also been investigated in order to tackle the challenges involved in nanoscale device design.