Programmable auxiliary co-processing unit for H.264 decoder
Programmable auxiliary co-processing unit for H.264 decoder
| dc.contributor.author | Peesapati, Rangababu | |
| dc.contributor.author | Sabat, Samrat L. | |
| dc.date.accessioned | 2022-03-27T06:43:06Z | |
| dc.date.available | 2022-03-27T06:43:06Z | |
| dc.date.issued | 2019-12-01 | |
| dc.description.abstract | This objective of the paper is to develop a hardware accelerator for H.264 video decoder. This can be achieved through H.264 decoder interfaced as an Auxiliary Processing Unit (APU) with the embedded PowerPC (PPC440) processor in System on Chip (SoC) platform on Xilinx Virtex-5 development board. The H.264 APU accelerator is tested with various video sequences and found 7x acceleration as compared to equivalent software execution and literature | |
| dc.identifier.citation | Proceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019 | |
| dc.identifier.uri | 10.1109/iSES47678.2019.00046 | |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/9002462/ | |
| dc.identifier.uri | https://dspace.uohyd.ac.in/handle/1/9895 | |
| dc.subject | Advanced Video Coding (AVC) | |
| dc.subject | Auxiliary Processing Unit(APU) | |
| dc.subject | Field Programmable Gate Array(FPGA) | |
| dc.subject | System on Chip(SoC) | |
| dc.title | Programmable auxiliary co-processing unit for H.264 decoder | |
| dc.type | Conference Proceeding. Conference Paper | |
| dspace.entity.type |
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