Performance evaluation of Hetero-Gate-Dielectric Re-S/D SOI MOSFET for low Power Applications

Abstract

Recently, Fully-depleted Silicon-on-Insulator (FD SOI) technology has been recognized for its immunity over short-channel-effects (SCEs) in nanoscale regime. This paper presents the impact of Hetero-Gate-Dielectric on the performance of triple-metal-gate recessed-source/drain (TMG Re-S/D) FD SOI MOSFET for low-power and high-performance applications. Here, for the first time, the effect of gate-oxide engineering has been monitored in the design of TMG Re-S/D FD SOI MOSFET. For this, the short-channel immunity of the studied MOSFET has been investigated on the basic of various performance parameters like, off-state leakage (Ioff), switching ratio (Ion/Ioff), subthreshold-behavior and threshold voltage roll-off. The device has been designed and simulated using numerical TCAD simulator from Silvaco. It has been observed that the proposed MOSFET offers better electrical performance as compared to other state-of-the-arts at 45nm technology node. Simultaneously, in order to optimize the design challenges at nanometer nodes, the impact of buried oxide (BOX) thickness variations on the performance of studied MOS structure has also been taken under study.