Hardware architecture of a digital piecewise linear chaotic map with perturbation for pseudorandom number generation

Abstract

Piecewise linear chaotic map (PWLCM) is a simple chaotic system popularly used for generating pseudorandom numbers (PRN). Digital implementation of PWLCM degrades the randomness of the pseudorandom number due to the finite precision effect. The current paper presents a digital 1-dimensional PWLCM that mitigates the degradation of digital chaos by cascading the chaotic map with a three-stage XORed shift register that perturbs the output of the PWLCM. We further perturb the output of the shift register using a one-stage XOR post-processing. We also present the hardware architecture of the proposed system to generate a high throughput PRN sequence. The designed architecture is synthesized on Xilinx Zynq 7000 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) using TSMC (Taiwan Semiconductor Manufacturing Company) 90 nm CMOS technology. We experimentally validate the randomness of the output sequence using NIST test suite 800–22. In addition, we also perform security analyses such as phase space, key sensitivity, correlation, and information entropy. The statistical and security analysis confirms the efficiency of the proposed design in terms of randomness. The synthesis result demonstrates the achieved throughput as 1.296 Gbps at 81 MHz operating frequency on Zynq 7000 FPGA, whereas a throughput of 1.696 Gbps at 106 MHz operating frequency is achieved on ASIC.