Design and analysis of nano-scaled SOI MOSFET-based ring oscillator circuit for high density ICs

Abstract

This paper presents the design and analysis of ring oscillator circuit based on nano-scaled SOI MOSFETs for low power applications. Recently, fully depleted silicon-on-insulator (FD SOI) MOSFETs have been recognised as the most viable technology at nanometer nodes. Therefore, it is necessary to analyze the electrical performance of SOI technology MOSFETs and their switching characteristics. In this contribution, firstly we have investigated the short channel immunity of dual metal insulated gate (DMIG) technique-based FD SOI MOSFET and its electrical characteristics has been compared and contrasted with the available state-of-arts. The device has been designed and simulated using numerical ATLAS SILVACO simulator. FD SOI technology along with DMIG technique found to be a better solution, and provide excellent performance (higher Ion/Ioff ratio, and lower sub-threshold slope) than other techniques reported at this node. Additionally, the detailed analysis of surface potential profile, electric field, electron concentration, and the contour plot of conduction current density have been taken into account. Further, for the first time, DMIG FD SOI MOSFET-based CMOS inverter and ring oscillator circuits have been designed using the same numerical simulator. DC and transient analysis itself explains that the designed CMOS inverter and ring oscillator offer lower voltage of operation with reduced power consumption, and high noise immunity. The oscillation frequency of ring oscillator is found as 84.18 GHz at 50 nm channel length.